The present invention relates generally to a semiconductor device and a method for fabricating the same, and more particularly to a technology for preventing a short phenomenon between a bump and a silicon (Si) of a semiconductor substrate during a through silicon via (TSV) process.
A three-dimensional stacking technique has been developed as a packaging technique in order to enhance a packaging density while reducing the size and improving performance of semiconductor devices. A three-dimensional stacking package is made by stacking a plurality of chips having the same memory capacity, which is referred to herein as a stacked chip package.
Mass production can lower the manufacturing cost of fabricating stacked chip packages. Initial use of the stacked packaging technique used wiring outside of the chip areas to connect stacked chips.
That is, chip layers in a conventional stacked chip packages are connected through wires coupled between a bonding pad of each chip and a conductive circuit pattern of a substrate while a plurality of chips are attached to a chip adhesion region of the substrate. As a result, a space for wire bonding is required, and a circuit pattern area of the substrate connected with the wire is also required so that the size of the semiconductor package is increased.
To overcome these size constraints, a structure using a through silicon via has been developed. After a through silicon via is formed within each chip in a bar wafer step, vertical physical and electrical connection between chips is facilitated by the through silicon via.
In a conventional process of forming a through silicon via, after a vertical hole is formed in a semiconductor substrate to obtain the through silicon via, the through silicon via is exposed by back-grinding the rear surface of the semiconductor substrate.
After the semiconductor substrate is separated into individual chips by sawing, at least two or more chips are vertically stacked over the semiconductor substrate so that signals may be exchanged through a conductive metal of the through silicon vias. The upper surface of the semiconductor substrate including the stacked chips is molded, and a shoulder ball is mounted on the lower surface of the semiconductor substrate, thereby completing the stacked package.
However, when a bump and a metal line connected with the through silicon via are formed, a contact surface between the bump and adjacent silicon may become misaligned, which results in a short.